The present invention relates to a semiconductor memory device using a flip-flop circuit as a data sensing means, and more particularly to a semiconductor memory device in which an improvement is made on the delay problem of a drive signal on the word line.
In the field of semiconductor memory devices, it has been recognized that a sense amplifier based on a flip-flop circuit has good sensitivity. It is for this reason that this type of sense amplifier has been widely used in dynamic RAMs (random access memories) of the open bit line system or the folded line system, EPROMs (erasable programmable read only memories), and EEPROMs (electrically erasable read only memories).
In FIG. 1, there is shown a latch sense amplifier of the open bit line system, which has been prevalently used in the memory device. A flip-flop 11 includes P- and N-channel MOS transistors. A pair of bit lines 12 and 14 are connected to both sides of the flip-flop 11, as shown. The bit line 12 as illustrated on the left side of the flip-flop 11 has a memory cell 13 connected thereto. The bit line 14 on the right side of the flip-flop 11 has a dummy cell 15. The memory cell 13 is of the EPROM type in which logical 1 or "0" of data is stored dependent on the conductance of the transistor contained therein. The conductance of the dummy cell 15 is selected to have an intermediate value between the two conductances of the memory cell 13 respectively corresponding to logical "1" and "0" stored therein.
In the flip-flop 11, during a precharge period, precharge transistors 18 and 19 and an equalizing transistor 20 are placed in an on-state. Potentials 21 and 22 on the pair of bit lines 12 and 14 are set at an equal potential, as shown in FIG. 2. At this time, the transistors 16 and 17 respectively inserted between the flip-flop 11 and a power source V.sub.DD and between the flip-flop 11 and a power source V.sub.SS, are in an off-state under the control of signals applied to the gates thereof. Under this condition, the flip-flop 11 is in an inactive state. In the inactive state of the flip-flop 11, if the precharging and the equalizing operations are stopped, a conductance difference between the memory cell 13 and the dummy cell 15 causes a potential difference .DELTA.V between the potentials 21 and 22 on the bit lines 12 and 14 (see FIG. 2). The potential difference .DELTA.V grows with time. When it becomes satisfactorily large, the transistors 16 and 17 are turned on to render the flip-flop 11 active in state. In the active state, the potential difference between the bit lines 12 and 14 is amplified by the flip-flop 11. The potential 22 on the bit line 14 in the low level rapidly becomes lower in level. The potential 21 on the bit line 12 in the high level becomes higher, rapidly.
In practical use, a number of the memory circuits shown in FIG. 1 are arrayed as shown in FIG. 3. A plurality of pairs of bit lines 12 and 14 are wired, as shown, and respectively coupled with sense amplifiers 30 each containing a flip-flop 11 and transistors 16 and 17 for controlling the active state of the flip-flop. Each bit line 12 is coupled with a memory cell 13. Each bit line 14 is coupled with a dummy cell 15. The gates of the transistors constituting the memory cells 13 are coupled together by word lines 32.sub.1 led from word line decoder/driver 31.sub.1. The gates of the transistors constituting the dummy cells 15 are coupled together by word lines 32.sub.2 led from word line decoder/driver 31.sub.2. Accordingly, decoded signals are applied from the decoder/driver 31.sub.1 to the gates of the transistors constituting the memory cells 13. Decoded signals are applied from the decoder/driver 31.sub.2 to the gates of the transistors constituting the dummy cells 15. Each of the word lines 32.sub.1 and 32.sub.2 is inevitably accompanied by parasitic resistance R and parasitic capacitance C.
The word lines 32.sub.1 and 32.sub.2 cross over the bit lines 12 and 14, respectively. In fabricating such a memory device by the IC technology, the word line 32 (expressing the word lines 32.sub.1 and 32.sub.2) must be made of material different from that of the bit line 12/14 (expressing the bit lines 12 and 14). Usually, aluminum is used for the bit line 12/14 and polycrystal silicon for the word line 32. The word line 32 made of polycrystal silicon has a higher resistivity than the bit line 12/14 made of metal such as aluminum. Therefore, a large parasitic capacitance is caused between the word line 32 made of polycrystal silicon and the substrate. Further, since the length of the word line 32 is relatively long, the resistance and capacitance parasitic on the word line 32 are large. Therefore, the drive signal transmitted through the word line 32 is progressively delayed. That is, the drive signal suffers from a called word line delay. This delay time is large, 40 ns to 50 ns, in the case of an EEPROM of 256 Kilo bits. Due to this word line delay, the time variation of a potential on the bit line 12/14 close to the decoder/driver 31 (expressing the decoder/drivers 31.sub.1 and 31.sub.2) during the precharge period is different from that on the bit line 12/14 far from the decoder/driver 31. Potentials on the bit lines 12 and 14 near the decoder/driver 31 start to fall earlier, as shown by curves 41 and 42 in FIG. 4, respectively. Potentials on the bit lines 12 and 14 far from the decoder/driver 31 start to fall later, as shown by curves 43 and 44 in FIG. 4, respectively. Thus, the start timing of the bit line potential change differs with the distance of the bit line from the word line decoder/driver 31. Therefore, in the conventional memory device, the timing to render the sense amplifiers 30 active must carefully be selected. To be more specific, if all of the sense amplifiers 30 are made active at time t1 in FIG. 4, the sense amplifier associated with the bit lines 12 and 14, far from the decoder/driver 31, operates for data sensing before a potential difference between these bit lines reaches a satisfactory value. At this time, this sense amplifier can not sense the data. In another case, if all of the sense amplifiers 30 are placed in the active state at time t2 in FIG. 4, both of the potentials 41 and 42 on the bit lines 12 and 14 close to the decoder/driver 31 fall to relatively low potentials. Therefore, also in this case, the sense amplifier 30 associated with these bit lines can not sense the data.
Since the conventional memory device makes all of the sense amplifiers 30 active concurrently, a large peak current flows through a circuitry between the power sources V.sub.DD and V.sub.SS. The peak current produces noise, and the power lines and signal lines of other circuits are floating, possibly causing the memory device to erroneously operate.